In general, a DLL refers to a circuit which generates multi-phase clock signals obtained by delaying a reference clock signal REF through a delay line.
FIG. 1 is a block diagram illustrating the configuration of a conventional DLL.
Referring to FIG. 1, the conventional DLL 30 includes a phase detector 31, a charge pump 32, a low-pass filter 33, a voltage controlled delay line (VCDL) 34. The phase detector 31 is configured to compare a N-th positive edge of a reference clock signal REF to an (N−1)-th positive edge of a feedback clock signal FEB, and output a phase difference signal UP/DOWN corresponding to the phase difference therebetween. The charge pump 32 is configured to generate a phase difference current corresponding to the phase difference signal UP/DOWN. The low-pass filter 33 is configured to convert the phase difference current into a voltage signal and generate a control voltage Vctrl. The VCDL 34 is configured to generate multi-phase clock signals by adjusting a delay time of the reference clock signal REF in response to the control voltage Vctrl.
The multi-phase clock signals include delayed clock signals obtained by delaying the reference clock signal REF by predetermined phase differences. Among the multi-phase clock signals, the final delayed clock signal which is synchronized with the reference clock signal REF by delaying the reference clock signal REF by one cycle becomes the feedback clock signal FEB provided to the phase detector 31.
FIG. 2 is a block diagram illustrating the configuration of the phase detector of FIG. 1.
Referring to FIG. 2, when the phase of the reference clock signal REF leads the phase of the feedback clock signal FEB, a first flip-flop FF1 first activates and outputs the up signal UP. A second flip-flop FF2 activates and outputs the down signal DOWN after a time based on the phase difference between the reference clock signal REF and the feedback clock signal FEB. An AND gate AD resets the first and second flip-flops FF1 and FF2 when both of the up signal UP and the down signal DOWN are activated.
When the phase of the feedback clock signal FEB leads the phase of the reference clock signal REF, the second flip-flop FF2 first activates and outputs the down signal DOWN. When the first flip-flop FF1 activates and outputs the up signal UP after a time based on the phase difference, the AND gate AD resets the first and second flip-flops FF1 and FF2.
When the phase of the reference clock signal REF is identical to the phase of the feedback clock signal FEB, the first and second flip-flops FF1 and FF2 activate the up signal UP and the down signal DOWN at the same time, and are reset by the AND gate AD. When the feedback clock signal FEB is delayed by one cycle from the reference clock signal REF and synchronized with the reference clock signal REF, the DLL 30 becomes in a normal lock state.
When designing the DLL 30, it is important to design the DLL 30 such that false lock does not occur. The false lock problem of the DLL 30 includes harmonic lock and stuck lock.
The harmonic lock refers to a state in which the DLL 30 maintains a false lock state when the delay time of the feedback clock signal FEB delayed from the reference clock signal REF corresponds to integer multiples of one cycle T1 of the reference clock signal REF, for example, two cycles T2, three cycles T3, and four cycles T4. In the harmonic lock state, the reference clock signal REF and the feedback clock signal FEB are synchronized without a difference phase. Therefore, the DLL 30 determines that the harmonic lock state is a normal lock state.
FIG. 3 is a timing diagram of multi-phase clock signals when the conventional DLL is in a normal lock state. FIG. 4 is a timing diagram of multi-phase clock signals when the conventional DLL is in a harmonic lock state (two cycles). FIG. 5 is a timing diagram of multi-phase clock signals when the conventional DLL is in another harmonic lock state (three cycles).
In FIGS. 3 to 5, the multi-phase clock signals include first to 14th delayed clock signals CLK1 to CLK14, and the 14th delayed clock signal becomes the feedback clock signal FEB obtained by finally delaying the reference clock signal REF. Arrows illustrated under the down signal DOWN indicate positive edges of the reference clock signal REF and the first to 14th delayed clocks CLK1 to CLK14. Here, the multi-phase clock signals including 14 delayed clock signals CLK1 to CLK14 was taken as an example, and phase differences between the respective arrows are equal to each other. Therefore, in a normal lock state as illustrated in FIG. 3, the phase difference corresponds to a value obtained by equally dividing one cycle 1T by 14. Furthermore, in the harmonic lock state of two cycles 2T as illustrated in FIG. 4, the phase difference corresponds to a value obtained by equally dividing two cycles 2T by 14. Furthermore, in the harmonic lock state of three cycles 3T as illustrated in FIG. 5, the phase difference corresponds to a value obtained by equaling dividing three cycles 3T by 14.
Referring to FIGS. 3 to 5, the phases of the reference clock signal REF and the feedback clock signal FEB commonly coincide with each other in the normal lock state and the harmonic lock state of the conventional DLL. Therefore, the conventional DLL may determine that both of the normal lock state and the harmonic lock state are a normal lock state.
The stuck lock occurs when the DLL 30 operates in a direction to continuously reduce the delay time even though the delay time of the VCDL 34 has already approached the minimum delay time. As described above, the phase detector 31 compares an N-th positive edge of the reference clock signal REF to an (N−1)-th positive edge of the feedback clock signal FEB, and generates the phase difference signal UP/DOWN. When the phase detector 31 falsely compares the reference clock signal REF to the feedback clock signal FEB and generates a false phase difference signal UP/DOWN, the stuck lock state occurs. For example, suppose that the control voltage Vctrl already approaches a power supply voltage VDD in a DLL where the VCDL 34 has a minimum delay time. In this case, for a normal operation, the phase detector 31 must increase the delay time by generating the down signal DOWN to decrease the control voltage Vctrl. However, when the phase detector 31 falsely compares the reference clock signal REF to the feedback clock signal FEB and generates the up signal UP to increase the control voltage Vctrl, the DLL 30 falls in the stuck lock state where the DLL 30 does not operate, because the control voltage Vctrl already approaches the power supply voltage VDD which is the maximum voltage and is fixed to the power supply voltage VDD.
FIG. 6 is a timing diagram of multi-phase clock signals, an abnormal signal, and a normal signal when the conventional DLL is in the stuck lock state. Here, a DLL where a VCDL has a minimum delay time when a control voltage is a power supply voltage is taken as an example.
Referring to FIG. 6, when the phase detector 31 compares an N-th positive edge of the reference clock signal REF to an (N−1)-th positive edge of the feedback clock signal FEB, the phase detector 31 may determine that the phase of the feedback clock signal FEB leads the phase of the reference clock signal REF, and output a normal signal as the down signal DOWN. In this case, the DLL 30 normally operates.
On the other hand, when the phase detector 31 compares the phases of the reference clock signal REF and the feedback clock signal FEB, the phase detector 31 may compare an N-th positive edge of the reference clock signal REF to an N-th positive edge of the feedback clock signal FEB, misjudge that the phase of the reference clock signal REF leads the phase of the feedback clock signal FEB, and output an abnormal signal as the up signal UP. In this case, the DLL 30 falls in the stuck lock state, and does not normally operate.
Although not illustrated in FIG. 6, the stuck lock may occur in a DLL where the VCDL 34 has a minimum delay time when the control voltage Vctrl is a ground voltage VSS.
When the control voltage Vctrl is the ground voltage VSS, the phase detector 31 must reduce the delay time by generating the up signal UP to increase the control voltage Vctrl, for a normal operation. However, when the phase detector 31 falsely compares the reference clock signal REF and the feedback clock signal FEB and generates the down signal DOWN to decrease the control voltage Vctrl, the DLL 30 falls in the stuck lock state where the DLL 30 does not operate, because the control voltage Vctrl already approaches the ground voltage VSS as the minimum voltage and is fixed to the ground voltage VSS.
FIG. 7 is a state diagram of the phase detector of the conventional DLL.
Referring to FIG. 7, when the phase of the reference clock signal REF leads the phase of the feedback clock signal FEB (Early REF), the up signal UP is activated to ‘1’, and when the phase of the feedback clock signal FEB leads the phase of the reference clock signal REF (Late REF), the down signal DOWN is activated to ‘1’. When the phases of the reference clock signal REF and the feedback clock signal FEB coincide with each other and are synchronized with each other (Same REF & FEB), the up signal UP and the down signal DOWN are finally deactivated to ‘0’ to maintain the lock state as it is. Referring to FIG. 7, however, it can be seen that the state diagram of the phase detector of the conventional DLL is not provided with a function for preventing false lock such as the harmonic lock or the stuck lock.
Recently, research has been actively conducted on a variety of methods for preventing false lock and expanding a lock range in a DLL. One of the methods is to use a phase detector having a reset circuitry (IEEE Journal of Solid-State Circuits, Vol. 37, No. 11, November 2002) (title: A low-power small-area +−7.28-ps-jitter 1-GHz DLL-based clock generator). Hereinafter, this paper is referred to as a reference document 1.
However, the method disclosed in the reference document 1 has limitations in that it must start from a time point where a delay time of a VCDL is the smallest before a DLL operates, and a delay range VCDL_delay of the VCDL must satisfy a condition of “0<VCDL_delay<1.5 cycle”.
Furthermore, in the method disclosed in the reference document 1, stuck lock may occur when the initial state of the DLL differs because of a certain reason or the phase detector falsely compares a feedback clock signal and a reference clock signal at least once because of various factors during the operation of the DLL.
Another method for preventing false lock and expanding a lock range in a DLL is to use a replica delay line (IEEE Journal of Solid-State Circuits, Vol. 35, No. 3, March 2002) (title: An all-analog multiphase delay-locked loop using replica delay line for wide-range operation and low-jitter performance). Hereinafter, this paper is referred to as a reference document 2.
The reference document 2 proposes a wide-range DLL using a replica delay line. In the method disclosed in the reference document 2, the replica delay line includes a current steering phase detector (CSPD) and a low-pass filter, and a current ratio of a charge pump of the CSPD must be set with precision.
However, the wide-range DLL proposed in the reference document 2 may be used only when a duty rate of a reference clock signal is a predetermined rate, for example, 50%, and the current ratio of a current pump used in the replica delay line must be designed with precision.